refactor: add test make jac

rspower/examples/test_make_jac.txt

+#include ../data/case14.txt
+#include ../lib/idx_gen.txt
+#include ../lib/idx_bus.txt
+#include ../lib/idx_brch.txt
+#include ../lib/make_y_bus.txt
+#include ../lib/make_jac.txt
+
+jac = make_jac(baseMVA, bus, branch, gen);
+return jac;

rspower/lib/make_jac.txt

-fn make_jac(bus, branch, gen, ybus) {
-
+fn make_jac(baseMVA, bus, branch, gen) {
+    // build Ybus
+    Ybus = make_y_bus(baseMVA, bus, branch);
+    
+    // extract voltage
+    V = slice(bus, [0], [VM-1,VM]) .* exp(c(0,1) * pi/180 * slice(bus, [0], [VA-1,VA]));
+    
+    // make sure we use generator setpoint voltage for PV and slack buses
+    on = find(slice(gen, [0], [GEN_STATUS-1, GEN_STATUS]) > 0);  // which generators are on?
+    gbus = get_multi(slice(gen, [0], [GEN_BUS-1, GEN_BUS]), on); // what buses are they at?
+    return gbus;
 }
\ No newline at end of file